{"id":35023,"date":"2026-07-02T05:21:06","date_gmt":"2026-07-02T03:21:06","guid":{"rendered":"https:\/\/www.chinasmartbuy.com\/blog\/imec-roadmap-chip-0-3nm-2038-cfet\/"},"modified":"2026-07-02T05:21:08","modified_gmt":"2026-07-02T03:21:08","slug":"imec-roadmap-chip-0-3nm-2038-cfet","status":"publish","type":"post","link":"https:\/\/www.chinasmartbuy.com\/blog\/imec-roadmap-chip-0-3nm-2038-cfet\/","title":{"rendered":"Imec aggiorna la roadmap dei chip: obiettivo 0,3 nm entro il 2038"},"content":{"rendered":"\n\n<style>\n  :root {\n    --red: #CC1B1B;\n    --red-light: rgba(204,27,27,0.08);\n    --red-mid: #e84040;\n    --accent-soft-bg: rgba(204,27,27,0.07);\n    --accent-soft-border: rgba(204,27,27,0.18);\n    --text: #1a1a1a;\n    --text-muted: #666;\n    --card: #ffffff;\n    --border: #ebebeb;\n    --page-bg: #ffffff;\n    --surface-soft: #fafafa;\n    --surface-contrast: #f0f0f0;\n    --line-soft: #f5f5f5;\n    --soft-label: #bbb;\n    --muted-label: #999;\n    --copy: #333;\n    --font-head: 'Bebas Neue', sans-serif;\n    --font-body: 'DM Sans', sans-serif;\n    --heading-spacing: 0.04em;\n    --heading-weight: 400;\n    --spec-header-spacing: 0.08em;\n    --quickfacts-shadow: 0 10px 24px rgba(15,23,42,0.06);\n  }\n  .fbp5-wrap,.fbp5-wrap * { box-sizing:border-box; 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}\n    .rh-downloadbox-link { width:100%; }\n    .rh-offerbox-head { flex-direction:column; }\n    .rh-offerbox-links { grid-template-columns:1fr; }\n    .rh-offer-inline-wrap { flex-direction:column; align-items:flex-start; }\n    .rh-offer-inline-cta { width:100%; }\n  }\n<\/style>\n<div class=\"fbp5-wrap rh-json-article\" id=\"rh-article-mr2xst4m-f9y24\" data-rh-article-type=\"news\" data-rh-site-profile=\"china-smart-buy\">\n  <div class=\"fbp5-intro\">\n    \n    <p>Imec ha aggiornato la propria roadmap tecnologica per i semiconduttori e indica un traguardo molto ambizioso: la possibilit\u00e0 di arrivare a processi produttivi di classe <strong>0,3 nm entro il 2038<\/strong>. Il centro di ricerca belga vede inoltre nei transistor <strong>CFET<\/strong> uno snodo chiave per continuare ad aumentare la densit\u00e0 dei chip nelle prossime generazioni.<\/p><p>La tabella di marcia \u00e8 stata definita con il contributo di nomi centrali dell&#8217;industria come TSMC, Intel, Nvidia, AMD, Samsung e ASML. Il messaggio di fondo \u00e8 chiaro: la miniaturizzazione non si fermer\u00e0 a breve, per\u00f2 dovr\u00e0 cambiare approccio tecnico perch\u00e9 la semplice riduzione laterale delle strutture sta arrivando ai propri limiti.<\/p>\n  <\/div><figure class=\"wp-block-image size-large\" style=\"margin:18px 0;display:block;clear:both;width:100%;position:relative;z-index:1\"><a href=\"https:\/\/www.chinasmartbuy.com\/blog\/wp-content\/uploads\/2026\/07\/imec-1ea7a6bc-1460-44d1-9af4-0e90-1a1rq3q9iv.webp\" target=\"_blank\" rel=\"noopener\" style=\"display:block;width:100%;position:relative;z-index:2;pointer-events:auto;cursor:zoom-in\"><img decoding=\"async\" src=\"https:\/\/www.chinasmartbuy.com\/blog\/wp-content\/uploads\/2026\/07\/imec-1ea7a6bc-1460-44d1-9af4-0e90-1a1rq3q9iv.webp\" alt=\"2038 \u5e74\u6709\u671b\u5b9e\u73b0 0.3nm \u5de5\u827a\u5236\u7a0b\uff0cimec \u516c\u5e03\u82af\u7247\u6280\u672f\u8def\u7ebf\u56fe\" loading=\"lazy\" style=\"display:block;max-width:100%;height:auto;margin:0 auto;pointer-events:auto\"><\/a><\/figure>\n  \n\n      <section class=\"fbp5-section\">\n        <div class=\"fbp5-section-label\">Roadmap<\/div>\n        <h2>La roadmap di imec punta a 0,3 nm e ridefinisce il <span>futuro della miniaturizzazione<\/span><\/h2>\n        <p>Oggi l&#8217;industria \u00e8 arrivata alla classe <strong>2 nm<\/strong>, con un contatto di gate tra transistor indicato attorno a 48 nm. Nel passaggio verso la classe A14, questo valore dovrebbe scendere a 45 nm, ma la roadmap mostra che oltre la classe A10, ci\u00f2\u00e8 intorno a 1 nm, il margine di riduzione si assottiglia in modo netto.<\/p><p>Dal 2030, con l&#8217;arrivo dei processi A10, il parametro CPP dovrebbe infatti fermarsi a <strong>42 nm<\/strong>. \u00c8 un passaggio importante perch\u00e9 segnala che il modello classico della legge di Moore, basato soprattutto sulla riduzione orizzontale delle dimensioni, non sar\u00e0 pi\u00f9 sufficiente da solo per aumentare la densit\u00e0 dei transistor come avvenuto finora.<\/p>\n        <ul class=\"fbp5-bullet-list\"><li>Obiettivo indicato dalla roadmap: processi di classe <strong>0,3 nm nel 2038<\/strong>.<\/li><li>Nodo intermedio ritenuto decisivo: <strong>0,7 nm nel 2033<\/strong>.<\/li><li>Stato attuale dell&#8217;industria: produzione gi\u00e0 arrivata alla classe <strong>2 nm<\/strong>.<\/li><li>CPP attuale vicino a <strong>48 nm<\/strong>, previsto a <strong>45 nm<\/strong> con A14 e poi stabilizzato a <strong>42 nm<\/strong> da A10.<\/li><\/ul>\n        <div class=\"rh-quickfacts-grid\">\n      <div class=\"rh-quickfacts-card\">\n        <div class=\"rh-quickfacts-label\">Ente che ha pubblicato la roadmap<\/div>\n        <div class=\"rh-quickfacts-value\">Imec<\/div>\n      <\/div>\n    \n      <div class=\"rh-quickfacts-card\">\n        <div class=\"rh-quickfacts-label\">Anno della roadmap<\/div>\n        <div class=\"rh-quickfacts-value\">2026<\/div>\n      <\/div>\n    <\/div>\n        <div class=\"fbp5-highlight\">La roadmap suggerisce che la prossima fase dell&#8217;evoluzione dei chip non dipender\u00e0 solo dalla riduzione delle dimensioni sul piano orizzontale.<\/div>\n        <div class=\"fbp5-info\">Per l&#8217;industria dei semiconduttori \u00e8 un segnale concreto: i progressi continueranno, ma con cambi architetturali pi\u00f9 profondi rispetto ai nodi precedenti.<\/div>\n        \n      <div class=\"fbp5-scheda\">\n        <div class=\"fbp5-scheda-header\">Tappe principali della roadmap<\/div>\n        \n          <div class=\"fbp5-scheda-row\">\n            <div class=\"fbp5-scheda-key\">Classe di processo attuale<\/div>\n            <div class=\"fbp5-scheda-val\">2 nm<\/div>\n          <\/div>\n        \n          <div class=\"fbp5-scheda-row\">\n            <div class=\"fbp5-scheda-key\">CPP attuale<\/div>\n            <div class=\"fbp5-scheda-val\">Circa 48 nm<\/div>\n          <\/div>\n        \n          <div class=\"fbp5-scheda-row\">\n            <div class=\"fbp5-scheda-key\">Classe A14<\/div>\n            <div class=\"fbp5-scheda-val\">CPP previsto a 45 nm<\/div>\n          <\/div>\n        \n          <div class=\"fbp5-scheda-row\">\n            <div class=\"fbp5-scheda-key\">Classe A10<\/div>\n            <div class=\"fbp5-scheda-val\">Circa 1 nm, CPP previsto a 42 nm<\/div>\n          <\/div>\n        \n          <div class=\"fbp5-scheda-row\">\n            <div class=\"fbp5-scheda-key\">Classe 0,7 nm<\/div>\n            <div class=\"fbp5-scheda-val\">Produzione attesa nel 2033<\/div>\n          <\/div>\n        \n          <div class=\"fbp5-scheda-row\">\n            <div class=\"fbp5-scheda-key\">Classe 0,3 nm<\/div>\n            <div class=\"fbp5-scheda-val\">Obiettivo indicato per il 2038<\/div>\n          <\/div>\n        \n      <\/div>\n    \n      <\/section>\n    \n\n      <section class=\"fbp5-section\">\n        <div class=\"fbp5-section-label\">Architettura<\/div>\n        <h2>I transistor CFET possono diventare il passaggio chiave dopo <span>FinFET e GAA<\/span><\/h2>\n        <p>Il cambio di passo individuato da imec \u00e8 l&#8217;adozione dell&#8217;architettura <strong>CFET<\/strong>, acronimo di transistor complementari a effetto di campo. In questo schema i transistor di tipo n e di tipo p non vengono pi\u00f9 disposti affiancati, ma impilati in verticale, aggiungendo cos\u00ec una nuova dimensione alla miniaturizzazione.<\/p><p>Questo approccio permetterebbe di usare lo spazio in modo pi\u00f9 efficiente e di continuare ad aumentare la densit\u00e0 dei transistor anche quando la riduzione laterale non offre pi\u00f9 vantaggi significativi. In prospettiva, la crescita dovrebbe passare soprattutto dalla riduzione dell&#8217;altezza delle celle e da una maggiore integrazione verticale.<\/p><p>Se il percorso verr\u00e0 confermato in produzione, CFET potrebbe diventare il nuovo standard dell&#8217;industria dopo i transistor <strong>FinFET<\/strong> e quelli <strong>GAA<\/strong>. Il fatto che realt\u00e0 come TSMC stiano gi\u00e0 lavorando su questa direzione rende la roadmap particolarmente rilevante perch\u00e9 anticipa dove si concentreranno investimenti, ricerca e capacit\u00e0 produttiva nei prossimi anni.<\/p>\n        <ul class=\"fbp5-bullet-list\"><li>CFET impila in verticale transistor di tipo n e p invece di collocarli fianco a fianco.<\/li><li>L&#8217;obiettivo \u00e8 superare i limiti della sola miniaturizzazione laterale.<\/li><li>La densit\u00e0 futura dei chip pu\u00f2 crescere grazie a integrazione verticale e riduzione dell&#8217;altezza delle celle.<\/li><li>CFET \u00e8 indicato come possibile successore delle architetture FinFET e GAA.<\/li><\/ul>\n        <div class=\"rh-quickfacts-grid\">\n      <div class=\"rh-quickfacts-card\">\n        <div class=\"rh-quickfacts-label\">Possibile anno di svolta produttiva<\/div>\n        <div class=\"rh-quickfacts-value\">2033<\/div>\n      <\/div>\n    \n      <div class=\"rh-quickfacts-card\">\n        <div class=\"rh-quickfacts-label\">Vantaggio principale<\/div>\n        <div class=\"rh-quickfacts-value\">Uso pi\u00f9 efficiente dello spazio sul chip<\/div>\n      <\/div>\n    <\/div>\n        <div class=\"fbp5-highlight\">Il vero salto non \u00e8 solo arrivare a 0,7 o <strong>0,3 nm<\/strong>, ma farlo con una struttura dei transistor capace di mantenere il ritmo di crescita della densit\u00e0.<\/div>\n        <div class=\"fbp5-info\">Per chi segue il settore, questa roadmap \u00e8 utile soprattutto perch\u00e9 mostra dove si giocher\u00e0 la competitivit\u00e0 dei prossimi chip: architettura del transistor, integrazione verticale e capacit\u00e0 di produzione sui nodi estremi.<\/div>\n        \n      <div class=\"fbp5-scheda\">\n        <div class=\"fbp5-scheda-header\">Confronto sintetico delle architetture<\/div>\n        \n          <div class=\"fbp5-scheda-row\">\n            <div class=\"fbp5-scheda-key\">FinFET<\/div>\n            <div class=\"fbp5-scheda-val\">Generazione gi\u00e0 affermata nella miniaturizzazione avanzata<\/div>\n          <\/div>\n        \n          <div class=\"fbp5-scheda-row\">\n            <div class=\"fbp5-scheda-key\">GAA<\/div>\n            <div class=\"fbp5-scheda-val\">Passo successivo gi\u00e0 avviato nei nodi pi\u00f9 recenti<\/div>\n          <\/div>\n        \n          <div class=\"fbp5-scheda-row\">\n            <div class=\"fbp5-scheda-key\">CFET<\/div>\n            <div class=\"fbp5-scheda-val\">Impilamento verticale di transistor n e p per nodi futuri<\/div>\n          <\/div>\n        \n      <\/div>\n    \n      <\/section>\n    \n<\/div><div class=\"rh-attribution-pills\" style=\"display:flex;gap:10px;flex-wrap:wrap;justify-content:flex-start;margin:16px 0 0\"><a href=\"https:\/\/www.ithome.com\/0\/971\/495.htm\" target=\"_blank\" rel=\"noopener\" title=\"Via: VIA\" aria-label=\"Via: VIA\" style=\"display:inline-flex;align-items:center;gap:8px;padding:10px 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